1. Field of the Invention
The present invention relates to a semiconductor storage device, and particularly to a technique for reducing standby current in a static semiconductor storage device, e.g., an SRAM (SRAM: Static Random Access Memory).
2. Description of the Related Art
SRAMs (typically, each memory cell includes six transistors to store one bit) are widely used for LSIs (LSI: Large Scale Integrated circuit). As regards SRAMs, a problem has become prominent in that leakage current increases in memory cells on standby, as a consequence of the reduced size and operation voltage of LSIs. The term “standby” means that a memory cell is in the non-selected state.
The thickness of the gate oxide film of MOSFETs (MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor) used in SRAMs is gradually decreasing, as LSIs are becoming more miniaturized and more highly integrated. As a consequence, the leakage current tunneling through the gate oxide film (gate leakage) increases and thereby brings about an increase in the total leakage current on standby. In addition, the threshold voltage of MOSFETs decreases along with decrease in the operation voltage of LSIs, which brings about an increase in the leakage current in the OFF-state (sub-threshold leakage).
As a countermeasure for reducing the standby leakage in SRAMs, there is a method of controlling the electric potential of a cell array on standby to relax an electric field applied to MOSFETs, in view of circuitry (for example, Masanao Yamaoka et al., “A 300 MHz 25 μA/Mb Leakage On-Chip SRAM Module . . . ”, ISSCC 2004/ SESSION 27/ SRAM/ 27.2, pp. 494-495). Further, as a related application filed by the same inventor, which has not yet been published, there is U.S. patent application Ser. No. 11/013,429, filed Dec. 17, 2004.